This invention relates generally to the field of integrated circuit fabrication, and more specifically to a system and method for annealing dielectric materials.
Metal oxide semiconductor (MOS) devices, including complementary MOS (CMOS) devices, have continued to decrease in size since their introduction many years ago. During this continuing decrease in feature size, various limitations to continued reduction in size have been encountered and-overcome. However, another such limitation, the thickness of the gate dielectric in a MOS device, is developing. The thickness of gate dielectrics has decreased over the years as new generations of smaller devices have been developed. In the past, silicon dioxide has typically been used as a gate dielectric. However, the continuing decrease in feature size and the resulting decrease in gate dielectric thickness suggests that silicon dioxide will soon no longer be an acceptable material for use as a gate dielectric. This is because the silicon dioxide used in these devices would have to be so thin that leakage current and other electrical defects become a significant problem.
One potential solution to this problem is to replace silicon dioxide (or other similar gate dielectric materials) with dielectric materials having a higher dielectric constant. Due to their higher dielectric constant (k), a thicker layer of such materials may be used to reduce the leakage current while providing similar gate capacitance and other benefits as a thinner layer of silicon dioxide. However, unlike silicon dioxide, such xe2x80x9chigh-kxe2x80x9d materials typically must be deposited as a film instead of being grown. Such deposited films are often not stoichiometric and have defects affecting their electrical properties.
According to the present invention, disadvantages and problems associated with previous systems and methods for annealing high dielectric constant materials have been substantially reduced or eliminated.
In one embodiment of the present invention, a method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650xc2x0 C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate.
Technical advantages of the present invention include the provisions of methods for annealing high-k gate dielectric layers that reduce or eliminate the formation of lower-k dielectric materials during the annealing process. Since high-k dielectric materials are often not stoichiometric and have defects affecting their electrical properties, these dielectric materials may be annealed to improve their electrical and physical characteristics and to properly oxidize the high-k gate dielectric material. However, many such annealing processes cause the growth of lower-k dielectric material due, at least in part, to the oxidizing environment. This lower-k dielectric material reduces the effectiveness of the high-k material used as the gate dielectric. Embodiments of the present invention reduce or eliminate the growth of these lower-k materials during the annealing process and thus improve the effectiveness of the high-k gate dielectric material while still allowing the dielectric material to be oxidized during the annealing process.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.